This invention relates to a semiconductor device and its manufacturing method, especially to a semiconductor device having a MIS (Metal-Insulator-Semiconductor) FET and its manufacturing method.
A power MISFET is one of many kinds of MIS gate semiconductors. And the power MISFET is in brisk demand for a main switching device in a switching circuit.
FIG. 35 is a cross-sectional view of the power MISFET active region as described in Japanese Patent Laid-Open No. 2001-298191. Also, FIG. 36 is a cross-sectional view of an enlarged electrode portion in scale.
In this MISFET there is provided an n-type pillar region 16 and a p-type pillar region 18 on an n+-type silicon substrate 12 in parallel and this parallel pairs are disposed in a successive form on the n+-type silicon substrate. A p+-type base region is provided on the p-type pillar region (on the opposite side of the n+-type silicon substrate), and also an n+-type source region 22 is provided thereon. A gate insulator film 24 is formed on the surface portion which includes the n-type pillar region, the n+-type source region and the p-type base region therebetween. A gate electrode 26 (control electrode) is formed on the gate insulator film 24. A side surface and an upper surface of the gate electrode 26 are protected for insulation by an inter-layer insulator 27. A portion of the p-type base region and a portion of the n-type source region are connected with a source electrode 28 (major electrode). On the other hand, a bottom surface of the n-type substrate is connected with a drain electrode 30 (other major electrode).
When an ON-voltage is supplied to the gate electrode 26, an inversion layer occurs on the surface of the p-type base region 20 facing the gate electrode via the gate insulator film 24, and hence a channel layer is formed. As a result, since the n-type source region and the n-type pillar region are connected, the main current can flow between the source electrode 28 and the drain electrode 30.
However, the Inventers found during a development that the above-mentioned device has a disadvantage as follows. If an avalanche break down occurs under a bonding pad for a gate electrode connection, an avalanche current concentrates in a part of the source region 22 adjacent to the bonding pad and hence an avalanche breakdown voltage is reduced.